Compact and low loss y-junction for submicron silicon waveguide

ABSTRACT

A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of co-pending U.S.provisional patent application Ser. No. 61/731,502, filed Nov. 30, 2012,which application is incorporated herein by reference in its entirety.

STATEMENT REGARDING FEDERALLY FUNDED RESEARCH OR DEVELOPMENT

This invention was made with government support under Grant NoFA9550-10-1-0053 awarded by the Air Force Office of Scientific Research(AFOSR). The government has certain rights in the invention.

FIELD OF THE INVENTION

The invention relates to optical waveguide components in general andparticularly to a Y-junction for use with submicron silicon waveguides.

BACKGROUND OF THE INVENTION

The last decade witnessed series of break-throughs in silicon photonics.Key components such as the electrically pumped laser (see, for example,R. Camacho-Aguilera, et al, “An electrically pumped germanium laser,”Opt. Express 20, 11316-11320 (2012)), the high-speed modulator (see, forexample, G. T. Reed, G. Mashanovish, F. Y. Gardes and D. J. Thomson,“Silicon optical modulators,” Nat. Photonics 4, 518-526 (2010)) and thephotodetector (see, for example, J. Michel, J. Liu, and L. C. Kimerling,“High-performance Ge-on-Si photodetectors,” Nat. Photonics, 4, 527- 534(2010)) have been successfully demonstrated. Foundry services are alsobecoming available to the community, making it easier to explore systemlevel functionalities (see, for example, Y. Zhang, T. Baehr-Jones, R.Ding, T. Pinguet, Z. Xuan, M. Hochberg, “Silicon multi-project waferplatforms for optoelectronic system integration,” Proc. 9th IEEE Intern.Conf. GFP, 2012, and the web sites of opsisfoundry.org and epixfab.eu).The intrinsic advantage of silicon as a photonic material system is itshigh refractive index contrast over silicon dioxide, allowing submicronwaveguides and tight bends, as well as the state-of-the-art CMOSfabrication infrastructure developed by the electronics industry.However, these two advantages do not always go in parallel. For example,a Y-junction is theoretically lossless, while this is generally not thecase due to limited resolution of micro fabrication. Sharp cornersfavored by photonics designs usually violate the minimum feature sizerule of a CMOS process, which can be easily caught by design rulechecking (DRC) routines. The possible detrimental effects of thisviolation in fabrication includes peeling off of photoresists, shalloweretch in the narrow gap, and voids in subsequent oxide claddingdeposition. All the above degrade device performance and lower yield.

A Y-junction formed by circular bends with a butt waveguide in betweento avoid the sharp corner has over 1 dB insertion loss. Mach-Zehndermodulators having two such Y-branches readily have more than 2 dBinsertion loss in the budget, regardless of other losses from freecarrier absorption and on-and-off chip light coupling, making them lesscompetitive to their III-V counterparts. In addition, complicatedintegrated optical circuits cannot be built on such lossy components.Moreover, the abrupt waveguide discontinuity causes light scattering andback-reflection. Implicit resonance cavities formed by these scatteringsites degrade the system spectrum response.

As one the most basic building blocks, a low loss and compact Y-junctionis very important for silicon photonic circuits. Recently a number ofauthors have demonstrated attractive device performance for Y-junctions(see, for example, A. Sakai, T. Fukazawa, and T. Baba, “Low lossultra-small branches in a silicon photonic wire waveguide,” IEICE Trans.Electron. E85-C, 1033-1038 (2002)), MMI couplers (see, for example, D.Van Thourhout, W. Bogaerts, P. Dumon, G. Roelkens, J. Van Campenhout, R.Baets, “Functional silicon wire waveguides,” Proc. Integrated PhotonicsResearch and Applications (2006)), cascaded splitters (see, for example,Z. Wang, Z. Fan, J. Xia, S. Chen and J. Yu, “1×8 cascaded multimodeinterference splitter in silicon-on-insulator,” Jpn. J. Appl. Phys. 43,5085-5087 (2004) and S. H. Tao, Q. Fang, J. F. Song, M. B. Yu, G. Q. Lo,and D. L. Kwong, “Cascaded wide-angle Y-junction 1×16 power splitterbased on silicon wire waveguides on silicon-on-insulator,” Opt. Express16, 21456-21461 (2008)), photonic crystal 3 dB couplers (see, forexample, L. H. Frandsen, et al, “Ultralow-loss 3 dB photonic crystalwaveguide splitter,” Opt. Lett. 29, 1623-1625 (2004)) and directionalcouplers (see, for example, H. Yamada, T. Chu, S. Ishida, and Y.Arakawa, “Optical directional coupler based on Si-wire waveguides,” IEEEPhotonics Technol. Lett. 17, 585-587 (2005)). However, a Y-junction withlow excess loss, low wavelength sensitivity, small footprint, anddimensions clearly within the typical design rules of a modern CMOSphotonics process has remained elusive.

The 1×3 power splitter function can be achieved by multi-modeinterference (MMI) couplers or directional couplers. Usually thesedevices have large insertion loss, large footprint, high wavelengthsensitivity or low compatibility with CMOS fabrication methods.

There is a need for an efficient Y-junction device that can bemanufactured easily.

SUMMARY OF THE INVENTION

According to one aspect, the invention features a 1×2 power splitter foruse in submicron silicon waveguides. The 1×2 power splitter comprises aninput port configured to receive an optical signal having a power ofsubstantially P watts; and a pair of output ports configured to providesubstantially equal output signals each having a power of substantiallyP/2 Watts; the 1×2 power splitter having a footprint of less than 1.2μm×2 μm in area.

In one embodiment, the input port has a taper width of 0.5 μm.

In another embodiment, at least one of the output ports has taper widthof 0.5 μm.

In yet another embodiment, the 1×2 power splitter has a total outputwidth of 1.2 μm.

In still another embodiment, the 1×2 power splitter has a minimumfeature size of 200 nm.

In a further embodiment, the 1×2 power splitter is configured to bemanufactured using a CMOS fabrication process.

In yet a further embodiment, the CMOS fabrication process is a processconducted using a 248 nm stepper.

In an additional embodiment, the CMOS fabrication process is a processconducted using a 193 nm stepper.

The foregoing and other objects, aspects, features, and advantages ofthe invention will become more apparent from the following descriptionand from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and features of the invention can be better understood withreference to the drawings described below, and the claims. The drawingsare not necessarily to scale, emphasis instead generally being placedupon illustrating the principles of the invention. In the drawings, likenumerals are used to indicate like parts throughout the various views.

FIG. 1A is a schematic diagram of the device layout.

FIG. 1B is a diagram showing the contour plot of the simulated electricfield intensity distribution at 1550 nm wavelength.

FIG. 2A is a graph showing the simulated power transmission as afunction of wavelength.

FIG. 2B is a graph showing the simulated reflection as a function ofwavelength.

FIG. 3A is a diagram showing the Y-junction characterization structurefor a plurality of cascaded Mach-Zehnder structures to measure insertionloss.

FIG. 3B is a diagram showing the Y-junction characterization structurefor a single Y-junction to measure coupling ratio and spectrum response.

FIG. 4A is a graph showing the typical measured spectra of the teststructure in FIG. 3A for different numbers of cascaded Mach-Zehnders.

FIG. 4B is a graph showing the typical measured spectra of the teststructure in FIG. 3B.

FIG. 5A is a graph of power loss as a function of the number ofY-junctions in a cascade. The dots are measured peak optical power fromtest structure in shown FIG. 3A on Die (0,0). The line is a linearfitting curve.

FIG. 5B is a plot of the measured cross-wafer insertion loss ofY-junctions.

DETAILED DESCRIPTION

We have designed a compact, low-loss and wavelength insensitiveY-junction for submicron silicon waveguide using FDTD and particle swarmoptimization (PSO), and fabricated the device in a 248 nm CMOS line. Wehave measured an average insertion loss of 0.28±0.02 dB across an 8-inchwafer. The device footprint is less than 1.2 μm×2 μm, orders ofmagnitude smaller than MMI and directional couplers. The function of theinvention is to provide a 1×2 power splitter for submicron siliconwaveguides.

Our device has very low loss, small footprint, low wavelengthsensitivity and was successfully fabricated by 248 nm CMOS with goodcross-wafer uniformity.

The device can be part of a more complicated optoelectronic device, suchas a Mach-Zehnder modulator, or a basic building block of integratedsilicon photonic circuit.

The device can be a useful component of the process design kit (PDK) ofa silicon photonics foundry. Companies commercializing silicon photonicstechnology, such as modulators and transceivers can also integrate thisdevice in their products.

The device achieves low loss, compact, and wavelength insensitive 1×2power splitting for submicron silicon waveguides. It interfaces with 500nm×200 nm silicon waveguide. The power splitter can be readily insertedinto other silicon photonic device or circuits as a basic buildingblock. It can be used as a standard GDS cell, similar to p-cells inelectronic circuit, such as transistors and resistors.

We modeled the electro-magnetic response of the structure using finitedifference time domain (FDTD) method, and optimized the device geometryusing particle swarm simulation (PSO).

We have designed and fabricated a Y-junction for submicron siliconwaveguide with a taper less than 1.2 μm×2 μm, and cross-wafer averageinsertion loss 0.28±0.02 dB, comparable to the result demonstrated byelectron beam lithography (EBL) and MMIs with much larger footprint. Thecoupling ratio is wavelength insensitive. The device has a minimumfeature size of 200 nm, and successfully fabricated using 248 nmlithography.

Design and Fabrication Design and Optimization

The goal was to design a compact, low loss and wavelength insensitiveY-junction for submicron silicon waveguide, compatible with typical CMOSphotonic processes, where 193 nm or 248 nm steppers are commonly used. Aminimum feature size of 200 nm was assumed during the design, which willnot break the designs rules, thus ensure yield. Silicon waveguidegeometry is 500 nm×220 nm. So the taper width is 0.5 μm at input and 1.2μm at output, as shown in FIG. 1A. The length of the taper connectinginput and output waveguides was set to 2 μm to keep the device compact.The size of Ge-on-Si photodetectors is usually on the order of 10 μm,and p-n junction modulator with phase shifter length of 50 μm has beendemonstrated (see, for example, H. C. Nguyen, S. Hashimoto, M. Shinkawaand T. Baba, “Compact and fast photonic crystal silicon opticalmodulators,” Opt. Express 20, 22465-22474 (2012)). A simple passivecomponent like Y-junction should be compact enough to be part of a morecomplicated active device or an integrated optical circuit. TheY-junction is symmetric in the propagation direction to ensure balancedoutput at two branches.

The electromagnetic response of dielectric structures of size on theorder of wavelength of interest can be simulated by Finite DifferenceTime Domain (FDTD) method. FDTD can be coupled with optimizationalgorithms to for design optimization. Sanchis et al demonstrated awaveguide crossing with 0.2 dB insertion loss and −40 dB cross-talkdesigned by FDTD and Genetic Algorithm (GA) (see, for example, P.Sanchis, et al, “Highly efficient crossing structure forsilicon-on-insulator waveguides,” Opt. Lett. 34, 2760-2762 (2009)). Weutilized a different optimization algorithm, Particle Swarm Optimization(PSO), in this design. PSO is initially inspired by the social behaviorof flocks of birds or schools of fish (see, for example, J. Kennedy andR. Eberhart, “Particle swarm optimization,” Proc. IEEE Intern. Conf.Neural Networks (1995)), and has been successfully applied toelectromagnetic optimization problems (see, for example, J. Robinson andY. Rhamat-Samii, “Particle swarm optimization in electromagnetics,” IEEETrans. Antennas Propag. 52,397-407 (2004)). In PSO, the potentialsolutions, called particles or agents, are initialized at randompositions with random velocities in the parameter space. A figure ofmerit function is defined to evaluate the particle position according tothe optimization goal. The best position for each individual particle isrecorded, as well as a global best position ever achieved by anyparticle in the swarm. The position of a particle is updated by thefollowing equation,

x _(n) =x _(n) +Δt*v _(n)   (1)

v _(n) =ω*v _(n) +c ₁*rand()*(p _(best,n) −x _(n))+c ₂*rand()*(g_(best,n) −x _(n))   (2)

where v_(n) and x_(n) are particle's velocity and position in nthdimension of the parameter space, and p_(best,n) and g_(best,n) areindividual and global best positions. As is apparent from Eq. 2, the newvelocity is the old velocity scaled by ω and increased the direction ofp_(best,n) and g_(best,n).

co , known as the inertial weight, is a measurement of how much aparticle would like to stay at the old velocity. c₁ determines how mucha particle is influenced by the memory of its best position, thussometimes called cognitive rates. And c₂ is a factor demining how muchthe particle is affected by the global best position of the whole swarm,hence called social rates. The two random numbers are used to simulatethe unpredictable behavior of natural swarm. It can be seen that theparticle velocity is large when it is far from p_(best,n) and g_(best,n), becomes smaller as it is closer to the best position and gets pulledback after flying over. The optimization is stopped when the figure ofmerit is good enough or a large number of iteration is reached.

FIG. 1A is a schematic diagram of the device layout.

FIG. 1B is a diagram showing the contour plot of the simulated electricfield intensity distribution at 1550 nm wavelength.

In this design, the taper was first digitalized into 13 segments ofequal length. The width of each segment, labeled as w1 to w13 in FIG.1A, was optimized to achieve low loss coupling. Taper geometry isdefined by spline interpolation of these 13 points. The optimizationfigure of merit (FOM) was the power in TEO mode at either branch. It wascalculated by the overlap integral of TEO mode of a 500 nm×220 nmwaveguide with the detected field at the output branch. Note that it isnot proper to set the total detected power to be FOM, since higher ordermodes will leak out of the waveguide along the way. Maximizing the powereffectively reduced the scattering and back-reflection. The swarmpopulation was set to 30. 2D FDTD was used as an approximation of 3DFDTD for computation efficiency during optimization. A commerciallyavailable code wad used (available fromhttp://www.lumerical.com/tcad-products/fdtd/ [16]. Within 50 iterations,one solution with sub-0.2 dB insertion loss emerged, as shown inTable 1. Then 3D FDTD was run on this solution to double check theresult with a mesh equal to 1/34 of the free space wavelength. Theinsertion loss was determined to be 0.13 dB. No noticeable scattering isseen in the contour plot of electric field intensity as shown in FIG. 1b. There is an interference pattern at the input end, indicatingnon-zero back-reflection. Due to the root square relationship betweenfield magnitude and optical intensity, very weak back-reflection isnecessary to create clear interference patterns. The normalizedtransmission and reflection power as a function of wavelength is plottedin FIG. 2A and FIG. 2B. It can be seen that both the transmission andreflection are wavelength insensitive, with variation below 1% and 0.5%over wavelength range from 1500 nm to 1580 nm.

TABLE 1 Taper width in μm w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 0.50.5 0.6 0.7 0.9 1.26 1.4 1.4 1.4 1.4 1.31 1.2 1.2

FIG. 2A is a graph showing the simulated power transmission as afunction of wavelength.

FIG. 2B is a graph showing the simulated reflection as a function ofwavelength.

Device Fabrication

Starting substrate was an 8-inch SOI wafer, with 220 nm, 10 ohm-cmp-type top silicon film, 2 μm buried oxide on top of a silicon handle.Waveguides were patterned using 248 nm UV lithography followed by dryetching. Then a few microns of oxide were deposited as top cladding.Light coupling on and off chip was achieved by grating couplers (GC).Two kinds of characterization structures are laid out, as shown in FIG.3A and FIG. 3B. A cascade of Mach-Zehnder structures formed by buttcoupled Y-junctions were used to measure the insertion loss, similarthose used in A. Mekis, et al, “A grating-coupler-enabled CMOS photonicsplatform,” IEEE J. Sel. Top. Quantum Electron. 17, 597-608 (2011). Theother structure has the three terminals of the Y-junction connected tothree grating couplers to measure the output directly. In both cases,the bend radius of waveguide is 10 μm. And grating coupler pitch is 127μm, determined by the pitch of fiber array. Simple GC loops, i.e. twoGCs connected by a U-turn waveguide, were used as a reference structure.Tiles used around the devices to achieve a certain filling ratio are notshown.

FIG. 3A is a diagram showing the Y-junction characterization structurefor a plurality of cascaded Mach-Zehnder structures to measure insertionloss.

FIG. 3B is a diagram showing the Y-junction characterization structurefor a single Y-junction to measure coupling ratio and spectrum response.

Results and Discussion Testing Configuration

Devices were measured on a wafer scale setup that can map the wafercoordinate to the stage coordinate, so that any device can be easilyprobed after initial alignment. Light from a tunable laser was coupledinto the device under test (DUT) via a though a polarization maintaining(PM) fiber and grating coupler, then to a photodetector through anothergrating coupler and PM fiber. Chuck temperature was set to 35° C.,slightly higher than room temperature. The device performance reportedin this paper is not expected as a strong function of temperature.Reticle size on the wafer is 2.5 cm×3.2 cm. Test structures shown inFIG. 3A and FIG. 3B in each die were tested to characterize thecross-wafer performance.

FIG. 4A is a graph showing the typical measured spectra of the teststructure in FIG. 3A for different numbers of cascaded Mach-Zehnders.

FIG. 4B is a graph showing the typical measured spectra of the teststructure in FIG. 3B.

Typical spectra structures in FIG. 3A and FIG. 3B are shown in FIG. 4Aand FIG. 4B respectively. The parabolic-like shape is determined by thegrating coupler spectrum response. The grating coupler design used hereworks only for TE mode and is highly polarization selective. Due to thenon-perfect polarization of input light, fringes appear on the spectra.The fringes are usually 0.5 dB peak to peak, and can be reduced by usinga polarization controller.

Device Performance

It is difficult to measure sub-0.5 dB insertion loss from a singledevice. Therefore, test structures with different numbers of Y-junctionsin the loop were used to figure out the insertion loss. The measuredpeak power as a function of number of Y-junctions in the loop is plottedin FIG. 5A. Dots are test data, and the line is linear fitting. Theslope of the line gives insertion loss in dB per Y-junction. Loopbaseline losses, such as grating coupler insertion loss, are the samefor all structures, thus won't affect the slope of the fitting line. Wemeasured the insertion loss of all Y-junctions across the wafer.

A contour plot of insertion loss is shown in FIG. 5B. From the contour,we can see that our device performance is uniform across the wafer, withan average of 0.28±0.02 dB. Low cross-wafer variation confirms that ourdevice is not fabrication sensitive, and can be reliable component of anintegrated photonic system.

We also note that the spectra of characterization structures in FIG. 4Ado not deviate from a reference GC spectrum, with only a linear offsetin y-axis, even with a large number of Y-junctions in the loop. Thisvalidates our estimation that although there is an interference patternin FIG. 1B the back-reflection is negligible and won't degrade thesystem spectrum response.

It is shown in S. H. Tao, Q. Fang, J. F. Song, M. B. Yu, G. Q. Lo, andD. L. Kwong, “Cascaded wide-angle Y-junction 1×16 power splitter basedon silicon wire waveguides on silicon-on-insulator,” Opt. Express 16,21456-21461 (2008) that etch residues or air voids in the gap defined bysharp corners in the layout will lead to non-uniform output at twobranches of the Y-junction. In FIG. 4B, the spectra of two branchesoverlaps over the whole testing wavelength range, indicating balancedoutput power. So our design fully addressed the DRC violation issue ofconventional Y-junctions.

The spectra in FIG. 4A and FIG. 4B also validate the simulation resultsin FIG. 2A and FIG. 2B, that the device performance is wavelengthinsensitive.

FIG. 5A is a graph of power loss as a function of the number ofY-junctions in a cascade. The dots are measured peak optical power fromtest structure in shown FIG. 3A on Die (0,0). The line is a linearfitting curve.

FIG. 5B is a plot of the measured cross-wafer insertion loss ofY-junctions.

Design Methodology

Our result also confirms PSO as an efficient optimization algorithm forsilicon photonic device design and optimization. We utilized moderateswarm population and iteration cycle. It is possible that even betterdevice geometry will emerge with more dedicated optimization. Thisdesign method can be readily used address other challenges such asnon-uniform grating couplers and distributed brag gratings (DBRs).

Optical Waveguides and Their Uses

We have described various optical waveguide systems and application, aswell as fabrication techniques for such waveguides in a number of patentdocuments, including U.S. Pat. Nos. 7,200,308, 7,424,192, 7,480,434,7,643,714, and 7,760,970.

Definitions

Unless otherwise explicitly recited herein, any reference to anelectronic signal or an electromagnetic signal (or their equivalents) isto be understood as referring to a non-volatile electronic signal or anon-volatile electromagnetic signal.

Recording the results from an operation or data acquisition, such as forexample, recording results at a particular frequency or wavelength isunderstood to mean and is defined herein as writing output data in anon-transitory manner to a storage element, to a machine-readablestorage medium, or to a storage device. Non-transitory machine-readablestorage media that can be used in the invention include electronic,magnetic and/or optical storage media, such as magnetic floppy disks andhard disks; a DVD drive, a CD drive that in some embodiments can employDVD disks, any of CD-ROM disks (i.e., read-only optical storage disks),CD-R disks (i.e., write-once, read-many optical storage disks), andCD-RW disks (i.e., rewriteable optical storage disks); and electronicstorage media, such as RAM, ROM, EPROM, Compact Flash cards, PCMCIAcards, or alternatively SD or SDIO memory; and the electronic components(e.g., floppy disk drive, DVD drive, CD/CD-R/CD-RW drive, or CompactFlash/PCMCIA/SD adapter) that accommodate and read from and/or write tothe storage media. Unless otherwise explicitly recited, any referenceherein to “record” or “recording” is understood to refer to anon-transitory record or a non-transitory recording.

As is known to those of skill in the machine-readable storage mediaarts, new media and formats for data storage are continually beingdevised, and any convenient, commercially available storage medium andcorresponding read/write device that may become available in the futureis likely to be appropriate for use, especially if it provides any of agreater storage capacity, a higher access speed, a smaller size, and alower cost per bit of stored information. Well known oldermachine-readable media are also available for use under certainconditions, such as punched paper tape or cards, magnetic recording ontape or wire, optical or magnetic reading of printed characters (e.g.,OCR and magnetically encoded symbols) and machine-readable symbols suchas one and two dimensional bar codes. Recording image data for later use(e.g., writing an image to memory or to digital memory) can be performedto enable the use of the recorded information as output, as data fordisplay to a user, or as data to be made available for later use. Suchdigital memory elements or chips can be standalone memory devices, orcan be incorporated within a device of interest. “Writing output data”or “writing an image to memory” is defined herein as including writingtransformed data to registers within a microcomputer.

“Microcomputer” is defined herein as synonymous with microprocessor,microcontroller, and digital signal processor (“DSP”). It is understoodthat memory used by the microcomputer, including for exampleinstructions for data processing coded as “firmware” can reside inmemory physically inside of a microcomputer chip or in memory externalto the microcomputer or in a combination of internal and externalmemory. Similarly, analog signals can be digitized by a standaloneanalog to digital converter (“ADC”) or one or more ADCs or multiplexedADC channels can reside within a microcomputer package. It is alsounderstood that field programmable array (“FPGA”) chips or applicationspecific integrated circuits (“ASIC”) chips can perform microcomputerfunctions, either in hardware logic, software emulation of amicrocomputer, or by a combination of the two. Apparatus having any ofthe inventive features described herein can operate entirely on onemicrocomputer or can include more than one microcomputer.

General purpose programmable computers useful for controllinginstrumentation, recording signals and analyzing signals or dataaccording to the present description can be any of a personal computer(PC), a microprocessor based computer, a portable computer, or othertype of processing device. The general purpose programmable computertypically comprises a central processing unit, a storage or memory unitthat can record and read information and programs using machine-readablestorage media, a communication terminal such as a wired communicationdevice or a wireless communication device, an output device such as adisplay terminal, and an input device such as a keyboard. The displayterminal can be a touch screen display, in which case it can function asboth a display device and an input device. Different and/or additionalinput devices can be present such as a pointing device, such as a mouseor a joystick, and different or additional output devices can be presentsuch as an enunciator, for example a speaker, a second display, or aprinter. The computer can run any one of a variety of operating systems,such as for example, any one of several versions of Windows, or ofMacOS, or of UNIX, or of Linux. Computational results obtained in theoperation of the general purpose computer can be stored for later use,and/or can be displayed to a user. At the very least, eachmicroprocessor-based general purpose computer has registers that storethe results of each computational step within the microprocessor, whichresults are then commonly stored in cache memory for later use, so thatthe result can be displayed, recorded to a non-volatile memory, or usedin further data processing or analysis.

Many functions of electrical and electronic apparatus can be implementedin hardware (for example, hard-wired logic), in software (for example,logic encoded in a program operating on a general purpose processor),and in firmware (for example, logic encoded in a non-volatile memorythat is invoked for operation on a processor as required). The presentinvention contemplates the substitution of one implementation ofhardware, firmware and software for another implementation of theequivalent functionality using a different one of hardware, firmware andsoftware. To the extent that an implementation can be representedmathematically by a transfer function, that is, a specified response isgenerated at an output terminal for a specific excitation applied to aninput terminal of a “black box” exhibiting the transfer function, anyimplementation of the transfer function, including any combination ofhardware, firmware and software implementations of portions or segmentsof the transfer function, is contemplated herein, so long as at leastsome of the implementation is performed in hardware.

Theoretical Discussion

Although the theoretical description given herein is thought to becorrect, the operation of the devices described and claimed herein doesnot depend upon the accuracy or validity of the theoretical description.That is, later theoretical developments that may explain the observedresults on a basis different from the theory presented herein will notdetract from the inventions described herein.

Any patent, patent application, patent application publication, journalarticle, book, published paper, or other publicly available materialidentified in the specification is hereby incorporated by referenceherein in its entirety. Any material, or portion thereof, that is saidto be incorporated by reference herein, but which conflicts withexisting definitions, statements, or other disclosure materialexplicitly set forth herein is only incorporated to the extent that noconflict arises between that incorporated material and the presentdisclosure material. In the event of a conflict, the conflict is to beresolved in favor of the present disclosure as the preferred disclosure.

While the present invention has been particularly shown and describedwith reference to the preferred mode as illustrated in the drawing, itwill be understood by one skilled in the art that various changes indetail may be affected therein without departing from the spirit andscope of the invention as defined by the claims.

1-8. (canceled)
 9. A method of designing a photonic device, the method comprising: identifying fabrication design rules of a fabrication process; generating an initial device design constrained by the fabrication design rules; and iteratively optimizing a device design starting with the initial device design.
 10. A method according to claim 9 wherein iteratively optimizing the device design comprises: generating a smoothed geometry of the device design; and simulating a functionality of the device utilizing the smoothed geometry of the device design.
 11. A method according to claim 10 wherein iteratively optimizing the device design comprises utilizing particle swarm optimization on the device design.
 12. A method according to claim 10 wherein generating the smoothed geometry of the device design comprises spline interpolation.
 13. A method according to claim 10 wherein iteratively optimizing the device design is performed in accordance with the fabrication design rules.
 14. A method according to claim 13 wherein the fabrication design rules comprise a minimum feature size.
 15. A method according to claim 10 wherein generating an initial device design comprises determining a plurality of I/O ports and segments along a direction of optical signal propagation, the plurality of segments characterized by a corresponding respective plurality of widths.
 16. A method according to claim 15 wherein iteratively optimizing the device design comprises utilizing an optimization algorithm on the plurality of widths.
 17. A method according to claim 16 wherein the optimization algorithm comprises a particle swarm optimization algorithm.
 18. A method according to claim 16 wherein the optimization algorithm comprises a genetic algorithm.
 19. A method according to claim 16 wherein simulating a functionality of the device comprises determining at least one figure of merit (FOM), wherein iteratively optimizing the device design comprises evaluating optimization criteria with use of the at least one FOM, and for each iteration of said iteratively optimizing for which optimization criteria has not been met, modifying at least one of the plurality of widths according to the optimization algorithm.
 20. A method according to claim 19 wherein simulating a functionality of the device comprises simulating the electromagnetic response of the device using a finite difference time domain (FDTD) method.
 21. A method according to claim 20 wherein generating a smoothed geometry of the device design comprises spline interpolation.
 22. A method according to claim 21 wherein the photonic device comprises a Y-junction and wherein the fabrication design rules comprise a minimum feature size of 200 nm.
 23. A method according to claim 22 wherein the at least one FOM comprises power in TEO mode at either branch. 